There are a variety of different applications that use programmable logic with hardware multiplexers forming part of the corresponding integrated circuits. Programmable logic devices (PLDs) (including PLDs in the form of System on Chip (SoC) devices) include programmable logic that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), can include an array of programmable tiles. These programmable tiles comprise various types of logic blocks, which can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay locked loops (DLLs), bus or network interfaces such as Peripheral Component Interconnect (PCI), PCI Express (PCIe) Ethernet, and so forth. Some PLDs include enough components and functionality to effectively serve as an entire computer system on a single IC chip. Devices with such functionality are sometimes referred to as SoCs.
Programming of PLDs often involves a design flow that begins with a design file(s) that defines the desired functionality of the PLDs. The design might then be synthesized to verify the design file relative to the destination PLD. The output of the synthesis can be a netlist. The netlist can then be used to implement the design using translation, mapping, placement, and routing. The result of these steps can be configuration data (e.g., in the form of bitstream file) that can be uploaded into the PLD for the purposed of configuring the programmable logic. Further steps might include the verification of design constraints, such as timing requirements for various signals. Designs that fail to meet the constraints might be rerun through the prior steps, which can add significant time to the process. Problems with meeting the constraints can be exacerbated by large designs that utilize a high percentage of the available programmable resources. For example, large designs can lead to routing congestion relating to limited programmable resources, such as the multiplexers used to implement configurable logic functions within the CLBs.
These and other problems can be problematic for IC design and their uses.